module ysyx_23060189_WBU #(parameter xlen = 32) (
  input wire           clk,
  input wire           rst,

  // data: MEU <=> WBU
  input  wire [xlen-1:0] me_inst,
  input  wire [xlen-1:0] me_pc,
  input  wire [1:0]      me_PC_sel,
  input  wire [1:0]      me_wb_sel,
  input  wire [2:0]      me_csr_cmd,
  input  wire            me_wb_en,
  input  wire            me_br_taken,
  input  wire [xlen-1:0] me_Alu_out,
  input  wire [4:0]      me_wb_addr,
  input  wire [xlen-1:0] me_rd_data,

  input  wire            me_valid,
  output wire            wb_ready,

  // data: WBU <=> IFU
  output wire [1:0]      wb_PC_sel,
  output wire [1:0]      wb_wb_sel,
  output wire            wb_wb_en,
  output wire            wb_br_taken,
  output wire [xlen-1:0] wb_csr_out,
  output wire [xlen-1:0] wb_Alu_out,
  output wire [4:0]      wb_wb_addr,
  output wire [xlen-1:0] wb_rd_data,

  output wire            wb_valid,
  input  wire            if_ready
);
  assign wb_PC_sel   = me_PC_sel;
  assign wb_wb_sel   = me_wb_sel;
  assign wb_wb_en    = me_wb_en;
  assign wb_br_taken = me_br_taken;
  assign wb_Alu_out  = me_Alu_out;
  assign wb_wb_addr  = me_wb_addr;
  assign wb_rd_data  = me_rd_data;

  assign wb_valid = me_valid;
  assign wb_ready = 1;

  ysyx_23060189_CSR CSR(
    .clk(clk),
    .rst(rst),
    .inst(me_inst),
    .pc(me_pc),
    .csr_cmd(me_csr_cmd),
    .csr_data(me_Alu_out),
    .csr_out(wb_csr_out)
  );

endmodule
